Side-channel analysis has become a widely recognized threat to the security of cryptographic implementations. Different side-channel attacks, as well as countermeasures, have been proposed in the literature. Such attacks pose a severe threat to both hardware and software cryptographic implementations, especially in the IoT environment where the attacker may easily gain physical access to a device, leaving it vulnerable to tampering. In this paper, we provide a comprehensive survey regarding the non-invasive passive side-channel analysis. We describe both non-profiled and profiled attacks, related security metrics, countermeasures against such attacks, and leakage-assessment methodologies, as available in the literature of more than twenty years of research.

Department of Digital Design Faculty of Information Technology Czech Technical University Prague 160 00 Prague Czech Republic

Zobrazit více v PubMed

Sicari S., Rizzardi A., Grieco L.A., Coen-Porisini A. Security, privacy and trust in Internet of Things: The road ahead. Comput. Netw. 2015;76:146–164. doi: 10.1016/j.comnet.2014.11.008. DOI

Daemen J., Rijmen V. The block cipher Rijndael; Proceedings of the International Conference on Smart Card Research and Advanced Applications; Louvain-la-Neuve, Belgium. 14–16 September 1998; Berlin/Heidelberg, Germany: Springer; 1998. pp. 277–284.

Advanced Encryption Standard. National Institute of Standards and Technology; Gaithersburg, MD, USA: 2001.

Rivest R.L., Shamir A., Adleman L. A method for obtaining digital signatures and public-key cryptosystems. Commun. ACM. 1978;21:120–126. doi: 10.1145/359340.359342. DOI

Kocher P.C. Timing attacks on implementations of Diffie-Hellman, RSA, DSS, and other systems; Proceedings of the Annual International Cryptology Conference; Santa Barbara, CA, USA. 18–22 August 1996; Berlin/Heidelberg, Germany: Springer; 1996. pp. 104–113.

Kocher P., Jaffe J., Jun B. Differential power analysis; Proceedings of the Annual International Cryptology Conference; Santa Barbara, CA, USA. 15–19 August 1999; Berlin/Heidelberg, Germany: Springer; 1999. pp. 388–397.

Quisquater J.J., Samyde D. Smart Card Programming and Security. Springer; Berlin/Heidelberg, Germany: 2001. Electromagnetic analysis (ema): Measures and counter-measures for smart cards; pp. 200–210.

Chari S., Jutla C.S., Rao J.R., Rohatgi P. Towards sound approaches to counteract power-analysis attacks; Proceedings of the Annual International Cryptology Conference; Santa Barbara, CA, USA. 15–19 August 1999; Berlin/Heidelberg, Germany: Springer; 1999. pp. 398–412.

Messerges T.S. Securing the AES finalists against power analysis attacks; Proceedings of the International Workshop on Fast Software Encryption; New York, NY, USA. 10–12 April 2000; Berlin/Heidelberg, Germany: Springer; 2000. pp. 150–164.

Nikova S., Rijmen V., Schläffer M. Secure hardware implementation of nonlinear functions in the presence of glitches. J. Cryptol. 2011;24:292–321. doi: 10.1007/s00145-010-9085-7. DOI

Gross H., Mangard S., Korak T. Domain-Oriented Masking: Compact Masked Hardware Implementations with Arbitrary Protection Order; Proceedings of the 2016 ACM Workshop on Theory of Implementation Security; Vienna, Austria. 24 October 2016; p. 3.

Tiri K., Akmal M., Verbauwhede I. A dynamic and differential CMOS logic with signal independent power consumption to withstand differential power analysis on smart cards; Proceedings of the 28th European Solid-State Circuits Conference; Florence, Italy. 24–26 September 2002; pp. 403–406.

Tiri K., Verbauwhede I. A logic level design methodology for a secure DPA resistant ASIC or FPGA implementation; Proceedings of the Design, Automation and Test in Europe Conference and Exhibition; Paris, France. 16–20 February 2004; pp. 246–251.

Güneysu T., Moradi A. Generic side-channel countermeasures for reconfigurable devices; Proceedings of the International Workshop on Cryptographic Hardware and Embedded Systems; Nara, Japan. 28 September–1 October 2011; Berlin/Heidelberg, Germany: Springer; 2011. pp. 33–48.

Mentens N., Gierlichs B., Verbauwhede I. Power and fault analysis resistance in hardware through dynamic reconfiguration; Proceedings of the International Workshop on Cryptographic Hardware and Embedded Systems; Washington, DC, USA. 10–13 August 2008; Berlin/Heidelberg, Germany: Springer; 2008. pp. 346–362.

Lisovets O., Knichel D., Moos T., Moradi A. Let’s take it offline: Boosting brute-force attacks on iPhone’s user authentication through SCA. IACR Trans. Cryptogr. Hardw. Embed. Syst. 2021;2021:496–519. doi: 10.46586/tches.v2021.i3.496-519. DOI

den Boer B., Lemke K., Wicke G. A DPA attack against the modular reduction within a CRT implementation of RSA; Proceedings of the International Workshop on Cryptographic Hardware and Embedded Systems; Redwood Shores, CA, USA. 13–15 August 2002; Berlin/Heidelberg, Germany: Springer; 2002. pp. 228–243.

Brier E., Clavier C., Olivier F. Correlation power analysis with a leakage model; Proceedings of the International Workshop on Cryptographic Hardware and Embedded Systems; Cambridge, MA, USA. 11–13 August 2004; Berlin/Heidelberg, Germany: Springer; 2004. pp. 16–29.

Chari S., Rao J.R., Rohatgi P. Template attacks; Proceedings of the International Workshop on Cryptographic Hardware and Embedded Systems; Redwood Shores, CA, USA. 13–15 August 2002; Berlin/Heidelberg, Germany: Springer; 2002. pp. 13–28.

Schellenberg F., Gnad D.R., Moradi A., Tahoori M.B. An inside job: Remote power analysis attacks on FPGAs; Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE); Dresden, Germany. 19–23 March 2018; pp. 1111–1116.

Zhao M., Suh G.E. FPGA-based remote power side-channel attacks; Proceedings of the 2018 IEEE Symposium on Security and Privacy (SP); San Francisco, CA, USA. 20–24 May 2018; pp. 229–244.

Standaert F.X. Secure Integrated Circuits and Systems. Springer; New York, NY, USA: 2010. Introduction to side-channel attacks; pp. 27–42.

Pant S. Ph.D. Thesis. The University of Michigan; Ann Arbor, MI, USA: 2008. Design and Analysis of Power Distribution Networks in VLSI Circuits.

Rabaey J.M. Digital Integrated Circuits: A Design Perspective. Pearson Education; Upper Saddle River, NJ, USA: 1996.

Horowitz P., Hill W., Robinson I. The Art of Electronics. Volume 2 Cambridge University Press; Cambridge, UK: 1989.

Gaubert P., Teramoto A. Different Types of Field-Effect Transistors: Theory and Applications. InTech; Rijeka, Croatia: 2017. Carrier mobility in field-effect transistors; pp. 2–25.

Rabaey J.M., Chandrakasan A.P., Nikolić B. Digital Integrated Circuits: A Design Perspective. Pearson Education, Incorporated; Saddle River, NJ, USA: 2003.

Mangard S., Oswald E., Popp T. Power Analysis Attacks: Revealing the Secrets of Smart Cards. Volume 31 Springer Science & Business Media; Berlin/Heidelberg, Germany: 2008.

Moradi A. Advances in Side-Channel Security. Ruhr-Universität Bochum; Bochum, Germany: 2015.

O’Flynn C., Chen Z. Synchronous sampling and clock recovery of internal oscillators for side channel analysis and fault injection. J. Cryptogr. Eng. 2015;5:53–69. doi: 10.1007/s13389-014-0087-5. DOI

Camurati G., Poeplau S., Muench M., Hayes T., Francillon A. Screaming channels: When electromagnetic side channels meet radio transceivers; Proceedings of the 2018 ACM SIGSAC Conference on Computer and Communications Security; Toronto, ON, Canada. 15–19 October 2018; pp. 163–177.

Afzali-Kusha A., Nagata M., Verghese N.K., Allstot D.J. Substrate noise coupling in SoC design: Modeling, avoidance, and validation. Proc. IEEE. 2006;94:2109–2138. doi: 10.1109/JPROC.2006.886029. DOI

Camurati G., Francillon A., Standaert F.X. Understanding screaming channels: From a detailed analysis to improved attacks. IACR Trans. Cryptogr. Hardw. Embed. Syst. 2020;2020:358–401. doi: 10.46586/tches.v2020.i3.358-401. DOI

Gnad D.R., Oboril F., Kiamehr S., Tahoori M.B. Analysis of transient voltage fluctuations in FPGAs; Proceedings of the 2016 International Conference on Field-Programmable Technology (FPT); Xi’an, China. 7–9 December 2016; pp. 12–19.

Ramesh C., Patil S.B., Dhanuskodi S.N., Provelengios G., Pillement S., Holcomb D., Tessier R. FPGA side channel attacks without physical access; Proceedings of the 2018 IEEE 26th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM); Boulder, CO, USA. 29 April–1 May 2018; pp. 45–52.

Gierlichs B., Batina L., Tuyls P., Preneel B. Mutual information analysis; Proceedings of the International Workshop on Cryptographic Hardware and Embedded Systems; Washington, DC, USA. 10–13 August 2008; Berlin/Heidelberg, Germany: Springer; 2008. pp. 426–442.

Standaert F.X., Malkin T.G., Yung M. A formal practice-oriented model for the analysis of side-channel attacks. IACR e-Print Arch. 2006;134:2.

Messerges T.S., Dabbish E.A., Sloan R.H. Examining smart-card security under the threat of power analysis attacks. IEEE Trans. Comput. 2002;51:541–552. doi: 10.1109/TC.2002.1004593. DOI

Oswald E., Mangard S., Herbst C., Tillich S. Practical second-order DPA attacks for masked smart card implementations of block ciphers; Proceedings of the Cryptographers’ Track at the RSA Conference; San Jose, CA, USA. 13–17 February 2005; Berlin/Heidelberg, Germany: Springer; 2006. pp. 192–207.

Johnson N.L., Kemp A.W., Kotz S. Univariate Discrete Distributions. Volume 444 John Wiley & Sons; Hoboken, NJ, USA: 2005.

Liu H., Qian G., Goto S., Tsunoo Y. AES key recovery based on Switching Distance model; Proceedings of the 2010 Third International Symposium on Electronic Commerce and Security; Nanchang, China. 29–31 July 2010; pp. 218–222.

Timon B. Non-profiled deep learning-based side-channel attacks with sensitivity analysis. IACR Trans. Cryptogr. Hardw. Embed. Syst. 2019;2019:107–131. doi: 10.46586/tches.v2019.i2.107-131. DOI

Bevan R., Knudsen E. Ways to enhance differential power analysis; Proceedings of the International Conference on Information Security and Cryptology; Seoul, Korea. 28–29 November 2002; Berlin/Heidelberg, Germany: Springer; 2002. pp. 327–342.

Canovas C., Clédière J. What do S-boxes say in differential side channel attacks? IACR Cryptol. ePrint Arch. 2005;2005:311.

Akkar M.L., Bevan R., Dischamp P., Moyart D. Power analysis, what is now possible…; Proceedings of the International Conference on the Theory and Application of Cryptology and Information Security; Kyoto, Japan. 3–7 December 2000; Berlin/Heidelberg, Germany: Springer; 2000. pp. 489–502.

Le T.H., Clédière J., Canovas C., Robisson B., Servière C., Lacoume J.L. A proposition for correlation power analysis enhancement; Proceedings of the International Workshop on Cryptographic Hardware and Embedded Systems; Yokohama, Japan. 10–13 October 2006; Berlin/Heidelberg, Germany: Springer; 2006. pp. 174–186.

Batina L., Gierlichs B., Lemke-Rust K. Comparative evaluation of rank correlation based DPA on an AES prototype chip; Proceedings of the International Conference on Information Security; Taipei, Taiwan. 15–18 September 2008; Berlin/Heidelberg, Germany: Springer; 2008. pp. 341–354.

Veyrat-Charvillon N., Standaert F.X. Mutual information analysis: How, when and why?; Proceedings of the International Workshop on Cryptographic Hardware and Embedded Systems; Lausanne, Switzerland. 6–9 September 2009; Berlin/Heidelberg, Germany: Springer; 2009. pp. 429–443.

Batina L., Gierlichs B., Prouff E., Rivain M., Standaert F.X., Veyrat-Charvillon N. Mutual information analysis: A comprehensive study. J. Cryptol. 2011;24:269–291. doi: 10.1007/s00145-010-9084-8. DOI

Silverman B.W. Density Estimation for Statistics and Data Analysis. Volume 26 CRC Press; Boca Raton, FL, USA: 1986.

Lemke-Rust K., Paar C. Gaussian mixture models for higher-order side channel analysis; Proceedings of the International Workshop on Cryptographic Hardware and Embedded Systems; Vienna, Austria. 10–13 September 2007; Berlin/Heidelberg, Germany: Springer; 2007. pp. 14–27.

Whitnall C., Oswald E. A comprehensive evaluation of mutual information analysis using a fair evaluation framework; Proceedings of the Annual Cryptology Conference; Santa Barbara, CA, USA. 14–18 August 2011; Berlin/Heidelberg, Germany: Springer; 2011. pp. 316–334.

Standaert F.X., Gierlichs B., Verbauwhede I. Partition vs. comparison side-channel distinguishers: An empirical evaluation of statistical tests for univariate side-channel attacks against two unprotected cmos devices; Proceedings of the International Conference on Information Security and Cryptology; Seoul, Korea. 3–5 December 2008; Berlin/Heidelberg, Germany: Springer; 2008. pp. 253–267.

Whitnall C., Oswald E., Standaert F.X. The myth of generic DPA… and the magic of learning; Proceedings of the Cryptographers’ Track at the RSA Conference; San Francisco, CA, USA. 25–28 February 2014; Cham, Switzerland: Springer; 2014. pp. 183–205.

Whitnall C., Oswald E., Mather L. An exploration of the kolmogorov-smirnov test as a competitor to mutual information analysis; Proceedings of the International Conference on Smart Card Research and Advanced Applications; Leuven, Belgium. 14–16 September 2011; Berlin/Heidelberg, Germany: Springer; 2011. pp. 234–251.

Maghrebi H., Rioul O., Guilley S., Danger J.L. Comparison between side-channel analysis distinguishers; Proceedings of the International Conference on Information and Communications Security; Hong Kong, China. 29–31 October 2012; Berlin/Heidelberg, Germany: Springer; 2012. pp. 331–340.

Cagli E., Dumas C., Prouff E. Convolutional neural networks with data augmentation against jitter-based countermeasures; Proceedings of the International Conference on Cryptographic Hardware and Embedded Systems; Taipei, Taiwan. 25–28 September 2017; Cham, Switzerland: Springer; 2017. pp. 45–68.

van der Valk D., Picek S., Bhasin S. Kilroy was here: The first step towards explainability of neural networks in profiled side-channel analysis; Proceedings of the International Workshop on Constructive Side-Channel Analysis and Secure Design; Lugano, Switzerland. 1–3 April 2020; Cham, Switzerland: Springer; 2020. pp. 175–199.

Rechberger C., Oswald E. Practical template attacks; Proceedings of the International Workshop on Information Security Applications; Jeju Island, Korea. 23–25 August 2004; Berlin/Heidelberg, Germany: Springer; 2004. pp. 440–456.

Choudary O., Kuhn M.G. Efficient template attacks; Proceedings of the International Conference on Smart Card Research and Advanced Applications; Berlin, Germany. 27–29 November 2013; Cham, Switzerland: Springer; 2013. pp. 253–270.

Kotsiantis S.B., Zaharakis I., Pintelas P. Supervised machine learning: A review of classification techniques. Emerg. Artif. Intell. Appl. Comput. Eng. 2007;160:3–24.

Hospodar G., Gierlichs B., De Mulder E., Verbauwhede I., Vandewalle J. Machine learning in side-channel analysis: A first study. J. Cryptogr. Eng. 2011;1:293. doi: 10.1007/s13389-011-0023-x. DOI

Heuser A., Zohner M. Intelligent machine homicide; Proceedings of the International Workshop on Constructive Side-Channel Analysis and Secure Design; Darmstadt, Germany. 3–4 May 2012; Berlin/Heidelberg, Germany: Springer; 2012. pp. 249–264.

Lerman L., Bontempi G., Markowitch O. Power analysis attack: An approach based on machine learning. Int. J. Appl. Cryptogr. 2014;3:97–115. doi: 10.1504/IJACT.2014.062722. DOI

Bartkewitz T., Lemke-Rust K. Efficient template attacks based on probabilistic multi-class support vector machines; Proceedings of the International Conference on Smart Card Research and Advanced Applications; Graz, Austria. 28–30 November 2012; Berlin/Heidelberg, Germany: Springer; 2012. pp. 263–276.

Lerman L., Poussier R., Markowitch O., Standaert F.X. Template attacks versus machine learning revisited and the curse of dimensionality in side-channel analysis: Extended version. J. Cryptogr. Eng. 2018;8:301–313. doi: 10.1007/s13389-017-0162-9. DOI

Benadjila R., Prouff E., Strullu R., Cagli E., Dumas C. Deep learning for side-channel analysis and introduction to ASCAD database. J. Cryptogr. Eng. 2020;10:163–188. doi: 10.1007/s13389-019-00220-8. DOI

Hettwer B., Gehrer S., Güneysu T. Applications of machine learning techniques in side-channel attacks: A survey. J. Cryptogr. Eng. 2020;10:135–162. doi: 10.1007/s13389-019-00212-8. DOI

Martinasek Z., Zeman V. Innovative method of the power analysis. Radioengineering. 2013;22:586–594.

Martinasek Z., Malina L., Trasy K. Computational Problems in Science and Engineering. Springer; Cham, Switzerland: 2015. Profiling power analysis attack based on multi-layer perceptron network; pp. 317–339.

Maghrebi H., Portigliatti T., Prouff E. Breaking cryptographic implementations using deep learning techniques; Proceedings of the International Conference on Security, Privacy, and Applied Cryptography Engineering; Hyderabad, India. 14–18 December 2016; Cham, Switzerland: Springer; 2016. pp. 3–26.

Kubota T., Yoshida K., Shiozaki M., Fujino T. Deep learning side-channel attack against hardware implementations of AES. Microprocess. Microsyst. 2020;87:103383. doi: 10.1016/j.micpro.2020.103383. DOI

Picek S., Heuser A., Jovic A., Bhasin S., Regazzoni F. The curse of class imbalance and conflicting metrics with machine learning for side-channel evaluations. IACR Trans. Cryptogr. Hardw. Embed. Syst. 2019;2019:1–29. doi: 10.46586/tches.v2019.i1.209-237. DOI

Standaert F.X., Malkin T.G., Yung M. A unified framework for the analysis of side-channel key recovery attacks; Proceedings of the Annual International Conference on the Theory and Applications of Cryptographic Techniques; Cologne, Germany. 26–30 April 2009; Berlin/Heidelberg, Germany: Springer; 2009. pp. 443–461.

Massey J.L. Guessing and entropy; Proceedings of the IEEE International Symposium on Information Theory; Trondheim, Norway. 27 June–1 July 1994; p. 204.

Köpf B., Basin D. An information-theoretic model for adaptive side-channel attacks; Proceedings of the 14th ACM Conference on Computer and Communications Security; Alexandria, VA, USA. 31 October–2 November 2007; pp. 286–296.

Fei Y., Luo Q., Ding A.A. A statistical model for DPA with novel algorithmic confusion analysis; Proceedings of the International Workshop on Cryptographic Hardware and Embedded Systems; Leuven, Belgium. 9–12 September 2012; Berlin/Heidelberg, Germany: Springer; 2012. pp. 233–250.

Heuser A., Rioul O., Guilley S. A theoretical study of Kolmogorov-Smirnov distinguishers; Proceedings of the International Workshop on Constructive Side-Channel Analysis and Secure Design; Paris, France. 13–15 April 2014; Cham, Switzerland: Springer; 2014. pp. 9–28.

Katz J., Lindell Y. Introduction to Modern Cryptography. CRC Press; Boca Raton, FL, USA: 2020.

Whitnall C., Oswald E. A fair evaluation framework for comparing side-channel distinguishers. J. Cryptogr. Eng. 2011;1:145–160. doi: 10.1007/s13389-011-0011-1. DOI

Mayhew M., Muresan R. An overview of hardware-level statistical power analysis attack countermeasures. J. Cryptogr. Eng. 2017;7:213–244. doi: 10.1007/s13389-016-0133-6. DOI

Matthews R. On the derivation of a “chaotic” encryption algorithm. Cryptologia. 1989;13:29–42. doi: 10.1080/0161-118991863745. DOI

Murillo-Escobar M.A., Cruz-Hernández C., Abundiz-Pérez F., López-Gutiérrez R.M. Implementation of an improved chaotic encryption algorithm for real-time embedded systems by using a 32-bit microcontroller. Microprocess. Microsyst. 2016;45:297–309. doi: 10.1016/j.micpro.2016.06.004. DOI

Majumder B., Hasan S., Uddin M., Rose G.S. Chaos computing for mitigating side channel attack; Proceedings of the 2018 IEEE International Symposium on Hardware Oriented Security and Trust (HOST); Washington, DC, USA. 30 April–4 May 2018; pp. 143–146.

Açikkapi M.Ş., Özkaynak F., Özer A.B. Side-channel analysis of chaos-based substitution box structures. IEEE Access. 2019;7:79030–79043. doi: 10.1109/ACCESS.2019.2921708. DOI

Beaulieu R., Shors D., Smith J., Treatman-Clark S., Weeks B., Wingers L. The SIMON and SPECK lightweight block ciphers; Proceedings of the 52nd Annual Design Automation Conference; San Francisco, CA, USA. 7–11 June 2015; pp. 1–6.

Aumasson J.-P., Bernstein D.J. SipHash: A fast short-input PRF; Proceedings of the International Conference on Cryptology in India; Kolkata, India. 9–12 December 2012; Berlin/Heidelberg, Germany: Springer; 2012. pp. 489–508.

Joseph M., Sekar G., Balasubramanian R. Side channel analysis of SPECK. J. Comput. Secur. 2020;28:655–676. doi: 10.3233/JCS-200021. DOI

Olekšák M., Miškovský V. Correlation Power Analysis of SipHash; Proceedings of the 2022 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS); Prague, Czech Republic. 6–8 April 2022; pp. 84–87.

Bucci M., Giancane L., Luzzi R., Trifiletti A. Three-phase dual-rail pre-charge logic; Proceedings of the International Workshop on Cryptographic Hardware and Embedded Systems; Yokohama, Japan. 10–13 October 2006; Berlin/Heidelberg, Germany: Springer; 2006. pp. 232–241.

Baddam K., Zwolinski M. Divided backend duplication methodology for balanced dual rail routing; Proceedings of the International Workshop on Cryptographic Hardware and Embedded Systems; Washington, DC, USA. 10–13 August 2008; Berlin/Heidelberg, Germany: Springer; 2008. pp. 396–410.

Razafindraibe A., Robert M., Maurine P. Improvement of dual rail logic as a countermeasure against DPA; Proceedings of the 2007 IFIP International Conference on Very Large Scale Integration; Atlanta, GA, USA. 15–17 October 2007; pp. 270–275.

Moon Y., Jeong D.K. An efficient charge recovery logic circuit. IEICE Trans. Electron. 1996;79:925–933.

Sana P.K., Satyam M. An energy efficient secure logic to provide resistance against differential power analysis attacks; Proceedings of the 2010 International Symposium on Electronic System Design; Bhubaneswar, India. 20–22 December 2010; pp. 61–65.

Choi B.D., Kim K.E., Chung K.S., Kim D.K. Symmetric adiabatic logic circuits against differential power analysis. ETRI J. 2010;32:166–168. doi: 10.4218/etrij.10.0209.0247. DOI

Avital M., Dagan H., Keren O., Fish A. Randomized multitopology logic against differential power analysis. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 2014;23:702–711. doi: 10.1109/TVLSI.2014.2320154. DOI

Bouesse G.F., Renaudin M., Dumont S., Germain F. DPA on quasi delay insensitive asynchronous circuits: Formalization and improvement; Proceedings of the Design, Automation and Test in Europe; Munich, Germany. 7–11 March 2005; pp. 424–429.

Bouesse F., Sicard G., Renaudin M. Path swapping method to improve DPA resistance of quasi delay insensitive asynchronous circuits; Proceedings of the International Workshop on Cryptographic Hardware and Embedded Systems; Yokohama, Japan. 10–13 October 2006; Berlin/Heidelberg, Germany: Springer; 2006. pp. 384–398.

Bouesse F., Renaudin M., Sicard G. Vlsi-Soc: From Systems To Silicon. Springer; Berlin/Heidelberg, Germany: 2007. Improving DPA resistance of quasi delay insensitive circuits using randomly time-shifted acknowledgment signals; pp. 11–24.

Zhu N., Zhou Y., Liu H. Counteracting leakage power analysis attack using random ring oscillators; Proceedings of the 2013 International Conference on Sensor Network Security Technology and Privacy Communication System; Harbin, China. 18–19 May 2013; pp. 74–77.

Kamoun N., Bossuet L., Ghazel A. Correlated power noise generator as a low cost DPA countermeasures to secure hardware AES cipher; Proceedings of the 2009 3rd International Conference on Signals, Circuits and Systems (SCS); Medenine, Tunisia. 6–8 November 2009; pp. 1–6.

Alipour A., Papadimitriou A., Beroulle V., Aerabi E., Hély D. On the performance of non-profiled differential deep learning attacks against an AES encryption algorithm protected using a correlated noise generation based hiding countermeasure; Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE); Grenoble, France. 9–13 March 2020; pp. 614–617.

Ratanpal G.B., Williams R.D., Blalock T.N. An on-chip signal suppression countermeasure to power analysis attacks. IEEE Trans. Dependable Secur. Comput. 2004;1:179–189. doi: 10.1109/TDSC.2004.25. DOI

Muresan R., Gregori S. Protection circuit against differential power analysis attacks for smart cards. IEEE Trans. Comput. 2008;57:1540–1549. doi: 10.1109/TC.2008.107. DOI

Hubert G.T. Current Source for Cryptographic Processor. 7,571,492. U.S. Patent. 2009 August 4;

Shamir A. Protecting Smart Cards from Power Analysis with Detachable Power Supplies. 6,507,913. U.S. Patent. 2003 January 14;

Tokunaga C., Blaauw D. Securing encryption systems with a switched capacitor current equalizer. IEEE J. Solid-State Circuits. 2009;45:23–31. doi: 10.1109/JSSC.2009.2034081. DOI

Mayhew M., Muresan R. On-chip nanoscale capacitor decoupling architectures for hardware security. IEEE Trans. Emerg. Top. Comput. 2014;2:4–15. doi: 10.1109/TETC.2014.2303934. DOI

Pedersen B.B. Programmable Logic Device with Improved Security. 8,255,702. U.S. Patent. 2012 August 28;

Clavier C., Coron J.S., Dabbous N. Differential power analysis in the presence of hardware countermeasures; Proceedings of the International Workshop on Cryptographic Hardware and Embedded Systems; Worcester, MA, USA. 17–18 August 2000; Berlin/Heidelberg, Germany: Springer; 2000. pp. 252–263.

Bucci M., Luzzi R., Guglielmo M., Trifiletti A. A countermeasure against differential power analysis based on random delay insertion; Proceedings of the 2005 IEEE International Symposium on Circuits and Systems; Kobe, Japan. 23–26 May 2005; pp. 3547–3550.

Jeřábek S., Schmidt J., Novotný M., Miškovský V. Dummy rounds as a DPA countermeasure in hardware; Proceedings of the 2018 21st Euromicro Conference on Digital System Design (DSD); Prague, Czech Republic. 29–31 August 2018; pp. 523–528.

Fumaroli G., Martinelli A., Prouff E., Rivain M. Affine masking against higher-order side channel analysis; Proceedings of the International Workshop on Selected Areas in Cryptography; Ontario, Canada. 12–13 August 2010; Berlin/Heidelberg, Germany: Springer; 2010. pp. 262–280.

Prouff E., Rivain M. Masking against side-channel attacks: A formal security proof; Proceedings of the Annual International Conference on the Theory and Applications of Cryptographic Techniques; Athens, Greece. 26–30 May 2013; Berlin/Heidelberg, Germany: Springer; 2013. pp. 142–159.

Mangard S., Pramstaller N., Oswald E. Successfully attacking masked AES hardware implementations; Proceedings of the International Workshop on Cryptographic Hardware and Embedded Systems; Edinburgh, UK. 29 August–1 September 2005; Berlin/Heidelberg, Germany: Springer; 2005. pp. 157–171.

Moos T., Moradi A., Schneider T., Standaert F.X. Glitch-resistant masking revisited. IACR Trans. Cryptogr. Hardw. Embed. Syst. 2019;2019:256–292. doi: 10.46586/tches.v2019.i2.256-292. DOI

Sasdrich P., Moradi A., Mischke O., Güneysu T. Achieving side-channel protection with dynamic logic reconfiguration on modern FPGAs; Proceedings of the 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST); Washington, DC, USA. 5–7 May 2015; pp. 130–136.

Akkar M.L., Giraud C. An implementation of DES and AES, secure against some attacks; Proceedings of the International Workshop on Cryptographic Hardware and Embedded Systems; Paris, France. 14–16 May 2001; Berlin/Heidelberg, Germany: Springer; 2001. pp. 309–318.

Trichina E., Korkishko T., Lee K.H. Small size, low power, side channel-immune AES coprocessor: Design and synthesis results; Proceedings of the International Conference on Advanced Encryption Standard; Bonn, Germany. 10–12 May 2004; Berlin/Heidelberg, Germany: Springer; 2004. pp. 113–127.

Oswald E., Mangard S., Pramstaller N., Rijmen V. A side-channel analysis resistant description of the AES S-box; Proceedings of the International Workshop on Fast Software Encryption; Paris, France. 21–23 February 2005; Berlin/Heidelberg, Germany: Springer; 2005. pp. 413–423.

Canright D., Batina L. A very compact “perfectly masked” S-box for AES; Proceedings of the International Conference on Applied Cryptography and Network Security; New York, NY, USA. 3–6 June 2008; Berlin/Heidelberg, Germany: Springer; 2008. pp. 446–459.

Nikova S., Rechberger C., Rijmen V. Threshold implementations against side-channel attacks and glitches; Proceedings of the International Conference on Information and Communications Security; Raleigh, NC, USA. 4–7 December 2006; Berlin/Heidelberg, Germany: Springer; 2006. pp. 529–545.

Moradi A., Poschmann A., Ling S., Paar C., Wang H. Pushing the limits: A very compact and a threshold implementation of AES; Proceedings of the Annual International Conference on the Theory and Applications of Cryptographic Techniques; Tallinn, Estonia. 15–19 May 2011; Berlin/Heidelberg, Germany: Springer; 2011. pp. 69–88.

Bilgin B., Gierlichs B., Nikova S., Nikov V., Rijmen V. A more efficient AES threshold implementation; Proceedings of the International Conference on Cryptology in Africa; Marrakesh, Morocco. 28–30 May 2014; Cham, Switzerland: Springer; 2014. pp. 267–284.

Bogdanov A., Knudsen L.R., Leander G., Paar C., Poschmann A., Robshaw M.J., Seurin Y., Vikkelsoe C. PRESENT: An ultra-lightweight block cipher; Proceedings of the International Workshop on Cryptographic Hardware and Embedded Systems; Vienna, Austria. 10–13 September 2007; Berlin/Heidelberg, Germany: Springer; 2007. pp. 450–466.

Sasdrich P., Bock R., Moradi A. Threshold implementation in software; Proceedings of the International Workshop on Constructive Side-Channel Analysis and Secure Design; Singapore. 23–24 April 2018; Cham, Switzerland: Springer; 2018. pp. 227–244.

Bilgin B., Gierlichs B., Nikova S., Nikov V., Rijmen V. Higher-order threshold implementations; Proceedings of the International Conference on the Theory and Application of Cryptology and Information Security; Kaoshiung, Taiwan, China. 7–11 December 2014; Berlin/Heidelberg, Germany: Springer; 2014. pp. 326–343.

Bilgin B., Gierlichs B., Nikova S., Nikov V., Rijmen V. Trade-offs for threshold implementations illustrated on AES. IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 2015;34:1188–1200. doi: 10.1109/TCAD.2015.2419623. DOI

Poschmann A., Moradi A., Khoo K., Lim C.W., Wang H., Ling S. Side-channel resistant crypto for less than 2300 GE. J. Cryptol. 2011;24:322–345. doi: 10.1007/s00145-010-9086-6. DOI

Schneider T., Moradi A., Güneysu T. Robust and one-pass parallel computation of correlation-based attacks at arbitrary order; Proceedings of the International Workshop on Constructive Side-Channel Analysis and Secure Design; Graz, Austria. 14–15 April 2016; Cham, Switzerland: Springer; 2016. pp. 199–217.

van Woudenberg J.G., Witteman M.F., Bakker B. Improving differential power analysis by elastic alignment; Proceedings of the Cryptographers’ Track at the RSA Conference; San Francisco, CA, USA. 14–18 February 2011; Berlin/Heidelberg, Germany: Springer; 2011. pp. 104–119.

Chu S., Keogh E., Hart D., Pazzani M. Iterative deepening dynamic time warping for time series; Proceedings of the 2002 SIAM International Conference on Data Mining; SIAM, Arlington, VA, USA. 11–13 April 2002; pp. 195–212.

Sauvage L., Guilley S., Danger J.L., Mathieu Y., Nassar M. Successful attack on an FPGA-based WDDL DES cryptoprocessor without place and route constraints; Proceedings of the 2009 Design, Automation & Test in Europe Conference & Exhibition; Nice, France. 20–24 April 2009; pp. 640–645.

Le T.H., Clédière J., Servière C., Lacoume J.L. Noise reduction in side channel attack using fourth-order cumulant. IEEE Trans. Inf. Forensics Secur. 2007;2:710–720. doi: 10.1109/TIFS.2007.910252. DOI

Souissi Y., Elaabid M.A., Debande N., Guilley S., Danger J.L. Novel applications of wavelet transforms based side-channel analysis; Proceedings of the Non-Invasive Attack Testing Workshop; Nara, Japan. 26–27 September 2011.

Debande N., Souissi Y., El Aabid M.A., Guilley S., Danger J.L. Wavelet transform based pre-processing for side channel analysis; Proceedings of the 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture Workshops; Vancouver, BC, Canada. 1–5 December 2012; pp. 32–38.

Ai J., Wang Z., Zhou X., Ou C. Improved wavelet transform for noise reduction in power analysis attacks; Proceedings of the 2016 IEEE International Conference on Signal and Image Processing (ICSIP); Beijing, China. 13–15 August 2016; pp. 602–606.

Messerges T.S. Using second-order power analysis to attack DPA resistant software; Proceedings of the International Workshop on Cryptographic Hardware and Embedded Systems; Worcester, MA, USA. 17–18 August 2000; Berlin/Heidelberg, Germany: Springer; 2000. pp. 238–251.

Prouff E., Rivain M., Bevan R. Statistical analysis of second order differential power analysis. IEEE Trans. Comput. 2009;58:799–811. doi: 10.1109/TC.2009.15. DOI

Waddle J., Wagner D. Towards efficient second-order power analysis; Proceedings of the International Workshop on Cryptographic Hardware and Embedded Systems; Cambridge, MA, USA. 11–13 August 2004; Berlin/Heidelberg, Germany: Springer; 2004. pp. 1–15.

Standaert F.X. How (not) to use welch’s t-test in side-channel security evaluations; Proceedings of the International Conference on Smart Card Research and Advanced Applications; Montpellier, France. 12–14 November 2018; Cham, Switzerland: Springer; 2018. pp. 65–79.

Gilmore R., Hanley N., O’Neill M. Neural network based attack on a masked implementation of AES; Proceedings of the 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST); Washington, DC, USA. 5–7 May 2015; pp. 106–111.

Goodwill G., Jun B., Jaffe J., Rohatgi P. A testing methodology for side-channel resistance validation; Proceedings of the NIST Non-Invasive Attack TESTING workshop; Nara, Japan. 26–27 September 2011; pp. 115–136.

Schneider T., Moradi A. Leakage assessment methodology; Proceedings of the International Workshop on Cryptographic Hardware and Embedded Systems; Saint-Malo, France. 13–16 September 2015; Berlin/Heidelberg, Germany: Springer; 2015. pp. 495–513.

Moradi A., Richter B., Schneider T., Standaert F.X. Leakage detection with the x2-test. IACR Trans. Cryptogr. Hardw. Embed. Syst. 2018;2018:209–237. doi: 10.46586/tches.v2018.i1.209-237. DOI

Moos T., Wegener F., Moradi A. DL-LA: Deep Learning Leakage Assessment. IACR Trans. Cryptogr. Hardw. Embed. Syst. 2021;2021:552–598. doi: 10.46586/tches.v2021.i3.552-598. DOI