A programmable logic controller (PLC) executes a ladder diagram (LD) using input and output modules. An LD also has PID controller function blocks. It contains as many PID function blocks as the number of process parameters to be controlled. Adding more process parameters slows down PLC scan time. Process parameters are measured as analog signals. The analog input module in the PLC converts these analog signals into digital signals and forwards them to the PID controller as inputs. In this research work, a field-programmable gate array (FPGA)-based multiple PID controller is proposed to retain PLC scan time at a lower value. Concurrent execution of multiple PID controllers was assured by assigning separate FPGA hardware resources for every PID controller. Digital input to the PID controller is routed by the novel idea of analog to digital conversion (ADC), performed using a digital to analog converter (DAC), comparator, and FPGA. ADC combined with dedicated PID controller logic in an FPGA for every closed-loop control system confirms concurrent execution of multiple PID controllers. The time required to execute two closed-loop controls was identified as 18.96000004 ms. This design can be used either with or without a PLC.
- Keywords
- PI control, analog to digital conversion, data acquisition, field programmable gate arrays, programmable logic controller, scan time,
- Publication type
- Journal Article MeSH
A low-cost Digital Signal Processor (DSP) unit for advanced Scanning Probe Microscopy measurements is presented. It is based on Red Pitaya board and custom built electronic boards with additional high bit depth AD and DA converters. By providing all the necessary information (position and time) with each data point collected it can be used for any scan path, using either existing libraries for scan path generation or creating adaptive scan paths using Lua scripting interface. The DSP is also capable of performing statistical calculations, that can be used for decision making during scan or for the scan path optimisation on the DSP level.
- Keywords
- Adaptive sampling, Field programmable gate array, Scanning probe microscopy,
- Publication type
- Journal Article MeSH
We report a non-blocking high-resolution digital delay line based on an asynchronous circuit design. Field-programmable gate array logic primitives were used as a source of delay and optimally arranged using combinatorial optimization. This approach allows for an efficient trade-off of the resolution and a delay range together with a minimized dead time operation. We demonstrate the method by implementing the delay line adjustable from 23 ns up to 1635 ns with a resolution of 10 ps. We present a detailed experimental characterization of the device focusing on thermal instability, timing jitter, and pulse spreading, which represent three main issues of the asynchronous design. We found a linear dependence of the delay on the temperature with the slope of 0.2 ps K-1 per logic primitive. We measured the timing jitter of the delay to be in the range of 7-165 ps, linearly increasing over the dynamic range of the delay. We reduced the effect of pulse spreading by introducing pulse shrinking circuits and reached the overall dead time of 4-22.5 ns within the dynamic range of the delay. The presented non-blocking delay line finds usage in applications where the dead time minimization is crucial, and tens of picoseconds of excess jitter is acceptable, such as in many advanced photonic networks.
- Publication type
- Journal Article MeSH
This paper introduces an enhancement to the Chen chaotic system by incorporating a constant perturbation term d to one of the state variables, aiming to improve the performance of pseudo-random number generators (PRNGs). The perturbation significantly enhances the system's chaotic properties, resulting in superior randomness and increased security. An FPGA-based realization of a perturbed Chen oscillator (PCO)-derived PRNG is presented, tailored for embedded cryptosystems and implemented on a Nexys 4 FPGA card featuring the XILINX Artix-7 XC7A100T-1CSG324C integrated chip. The Xilinx-based system generator (XSG) tool is utilized to generate a digital version of the new oscillator, minimizing resource utilization. Experimental results demonstrate that the PCO-generated data successfully passes the NIST and TestU01 test suites. Additionally, statistical tests with key sensitivity are performed, validating the suitability of the designed PRNG for cryptographic applications. This establishes the PCO as a straightforward and efficient tool for multimedia security.
We designed a simple, portable, low-cost and low-weight nondispersive infrared (NDIR) spectroscopy-based system for continuous remote sensing of atmospheric methane (CH4) with rapidly pulsed near-infrared light emitting diodes (NIR LED) at 1.65 μm. The use of a microcontroller with a field programmable gate array (μC-FPGA) enables on-the-fly and wireless streaming and processing of large data streams (~2 Gbit/s). The investigated NIR LED detection system offers favourable limits of detection (LOD) of 300 ppm (±5%) CH4,. All the generated raw data were processed automatically on-the-fly in the μC-FPGA and transferred wirelessly via a network connection. The sensing device was deployed for the portable sensing of atmospheric CH4 at a local landfill, resulting in quantified concentrations within the sampling area (ca 400 m2) in the range of 0.5%-3.35% CH4. This NIR LED-based sensor system offers a simple low-cost solution for continuous real-time, quantitative, and direct measurement of CH4 concentrations in indoor and outdoor environments, yet with the flexibility provided by the custom programmable software. It possesses future potential for remote monitoring of gases directly from mobile platforms such as smartphones and unmanned aerial vehicles (UAV).
This paper aims to evaluate detection algorithms for perimeter security systems based on phase-sensitive optical time-domain reflectometry (Φ-OTDR). Our own designed and developed sensor system was used for the measurement. The main application of the system is in the area the perimeter fencing intrusion detection. The system is unique thanks to the developed motherboard, which contains a field-programmable gate array (FPGA) that takes care of signal processing. This allows the entire system to be integrated into a 1U rack chassis. A polygon containing two different fence types and also cable laid underground in a plastic tube was used for testing. Edge detection algorithms using the Sobel and Prewitt operators are considered for post-processing. The comparison is made based on the signal-to-noise ratio (SNR) values calculated for each event. Results of algorithms based on edge detection methods are compared with the conventional differential method commonly used in Φ-OTDR systems.
- Keywords
- edge detection, intruder detection, phase-OTDR, signal-to-noise ratio, vibration sensing,
- Publication type
- Journal Article MeSH
This work is focused on creating an open-source software-based solution for monitoring traffic transmitted through gigabit passive optical network. In this case, the data are captured by the field-programmable gate array (FPGA) card and reassembled using parsing software from a passive optical network built on the International Telecommunication Unit telecommunication section (ITU-T) G.984 gigabit-capable passive optical network GPON recommendation. Then, the captured frames are converted by suitable software into GPON frames, which will be further processed for analysis. Due to the high transfer rate of GPON recommendations, the work describes the issue of writing to the Mongo database system. In order to achieve the best possible results and minimal loss of transmitted frames, a series of tests were performed. The proposed test scenarios are based on different database writing approaches and are implemented in the Python and C# programming languages. Based on our results, it has been shown that the high processing speed is too high for Python processing. Critical operations must be implemented in the C# programming language. Due to rapid application development, Python can only be used for noncritical time-consuming data processing operations.
As the ongoing standardization process of post-quantum schemes yields initial outcomes, it becomes increasingly important to not only optimize standalone implementations but also explore the potential of combining multiple schemes into a single, unified architecture. In this article, we investigate the combination of two National Institute of Standards and Technology (NIST)-selected schemes: the Dilithium digital signature scheme and the Kyber key encapsulation mechanism. We propose a novel set of optimization techniques for a unified hardware implementation of these leading post-quantum schemes, achieving a balanced approach between area efficiency and high performance. Our design demonstrates superior resource efficiency and performance compared to previously reported unified architecture (DOI 10.1109/TCSI.2022.3219555), also achieving results that are better than, or comparable, to those of standalone implementations. The efficient and combined implementation of lattice-based digital signatures and key establishment methods can be deployed for establishing secure sessions in high-speed communication networks at servers and gateways. Moreover, the unique and compact design that requires small hardware resources can be directly used in small and cost-effective field programmable gate array (FPGA) platforms that can be used as security co-processors for embedded devices and in the Internet of Things.
- Keywords
- Dilithium, FPGA, Kyber, Post-quantum cryptography, Unified architecture,
- Publication type
- Journal Article MeSH
A novel approach for multi-wavelength ultraviolet (UV) absorbance detection has been introduced employing a single board computer (SBC) with a field programmable gate array (FPGA), Red Pitaya SBC, to generate separated micro pulses for three deep-ultraviolet light-emitting diodes (DUV-LEDs), λmax = 235, 250, and 280 nm, along with data acquisition and processing via a custom-made program. The pulse set generation and data acquisition were synchronized using the SBC. The outputs of the three pulsing DUV-LEDs were combined and transmitted to the flow cell via a solarisation resistant trifurcated optical fiber (OF). An ultra-fast responding photodiode was connected to the optical-fiber-compatible flow cell to record the intensity of the DUV pulses. Upper limit of detector linearity (A95 %) was found to be 1917 mAU, 2189 mAU, and 1768 mAU at 235 nm, 250 nm, and 280 nm, respectively, with stray light ≤0.9 %. In addition, the effective path length (Leff) was estimated to be ≥98.0 % of the length of the used flow cell (50 mm). The new pulsed multi-LEDs absorbance detector (PMLAD) has been successfully coupled with a standard liquid chromatograph and utilized for the analysis of pharmaceuticals. Paracetamol, caffeine, and aspirin were simultaneously determined at 250, 280, and 235 nm, respectively, using the PMLAD. The absorbance ratios between the different wavelengths were applied to further confirm the identity of the studied compounds. Excellent linearity was achieved over a range of 0.1-3.2 µg/mL for paracetamol, 0.4-6.4 µg/mL for caffeine, and 0.8-12.8 µg/mL for aspirin with a regression correlation coefficient (r2) ≥ 0.99996. The quantitation limits (LOQs) were 0.10 µg/mL, 0.38 µg/mL, and 0.66 µg/mL for paracetamol, caffeine, and aspirin, respectively.
- Keywords
- Deep-ultraviolet absorption, High performance liquid chromatography, Multi-wavelength detection, Pulsing light-emitting diodes, Red Pitaya,
- MeSH
- Aspirin MeSH
- Chromatography, Liquid MeSH
- Caffeine * MeSH
- Acetaminophen MeSH
- Ultraviolet Rays * MeSH
- Publication type
- Journal Article MeSH
- Names of Substances
- Aspirin MeSH
- Caffeine * MeSH
- Acetaminophen MeSH
